(1) Field of the Invention
The present invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of forming a MOS gate electrode having a width not limited by photolithography resolution in the fabrication of integrated circuits.
(2) Description of the Prior Art
In the fabrication of integrated circuits, photolithography and etching are used to form structures such as polysilicon gates, word lines, bit lines, local oxidation of silicon (LOCOS), shallow trench isolation (STI), and the like. A photoresist material is coated over the layer or layers to be etched. The photoresist material is exposed to actinic light through a mask, then developed to form the photoresist mask for etching the underlying layer or layers. Using optical lithography, a resolution as small as 0.13 microns can be achieved. For smaller feature sizes, electron beam or X-ray lithography is necessary. However, these types of photolithography are expensive and time-consuming. It is desired to find a way to achieve a controllable gate electrode having a width not limited by photolithographic resolution.
U.S. Pat. No. 5,597,764 to Venkatesan et al teaches a method of forming a self-aligned gate within a recess. U.S. Pat. No. 5,734,185 to Ignuchi et al discloses a method of forming a polysilicon gate between dielectric spacers. U.S. Pat. No. 5,667,632 to Burton et al teaches forming and removing a dielectric spacer and forming a polysilicon gate within the spacer recess. U.S. Pat. No. 5,202,272 to Hsieh et al shows a gate process where a polysilicon layer is etched to form a spacer. There is a silicon nitride layer over the spacer. U.S. Pat. No. 4,419,809 to Riseman et al also discloses a poly spacer method including multiple oxidations and a masked etching process. U.S. Pat. No. 4,931,137 to Sibuet teaches forming poly spacers on a block which is then removed to leave poly gates. U.S. Pat. No. 5,593,813 to Kim shows a microscopic patterning process. U.S. Pat. No. 5,705,414 to Lustig shows a poly spacer on a stepped TEOS layer used as a mask to etch an underlying poly layer. U.S. Pat. No. 5,916,821 to Kerber teaches silicon nitride spacers on TEOS as a mask to etch a poly layer. U.S. Pat. No. 5,923,981 to Qian teaches spacers used as a mask to etch poly. U.S. Pat. No. 5,663,590 to Kapoor shows a process where metal spacers are used to connect overlying metal lines.